Understanding Computer Memory Architecture and SSD Internals
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39 min read2 days ago--Press enter or click to view image in full sizeMemory is a hardware component that stores binary information in blocks. Every memory device stores data as a sequence of binary digits (1s and 0s). Memory often appears as one continuous address space, but physical computer systems are built from multiple memory technologies arranged in a hierarchy. Each technology has its own form factor and involves trade-offs among capacity, access latency, bandwidth, power consumption, and manufacturing cost. Memory elements retain information over time, allowing digital systems to preserve state and execute sequential operations.Every piece of information processed inside a computer eventually resides in some form of memory.
Program instructions, variables, images, cryptographic keys, network packets, and intermediate computation results are all represented as binary values stored within a memory device.Common Characteristics of MemoryZero access latencyNon-volatile data retentionLow power consumptionUnlimited storage capacityMemory StructureA memory is represented as a large rectangular area with width and depth. The width represents the number of bits that can be allocated to a single memory block index, and depth defines the number of data-block locations.For example: If a data-bit is 8-bit wide and stored in 128 locations, then the total memory bits are 128 x 8 = 1024 bits.Press enter or click to view image in full sizeMemory capacity is determined by WIDTH x DEPTHMemory OperationsEvery memory device supports two fundamental operationsRead: retrieves the data stored at a specified memory address.Write: stores new data at a specified memory address.Common memory interfacesAddress BusData BusRead EnableWrite EnableClock (for synchronous memories)Memory HierarchyIn the previous section, I have described memory as a rectangular storage structure organized by its width and depth.
This representation is useful for understanding how data is stored but it does not accurately describe how memory is organized within a modern computer system.A general-purpose computer does not contain a single memory device. Instead, it consists of multiple memory technologies, each designed to satisfy different requirements for performance, capacity, access latency, and manufacturing cost. These memory technologies are organized into a memory hierarchy, where each level balances storage capacity and access speed differently.Press enter or click to view image in full sizeWhen a processor executes a program, it continuously requests instructions and data from memory. The processor first checks the smallest, fastest memory closest to the execution units rather than accessing main memory directly. If the requested data is not available, the request is forwarded to the next level of the hierarchy.
These memories are arranged into a memory hierarchy, where each level serves specific speeds and sizes.Press enter or click to view image in full sizeCPU Cache ArchitectureOne of the simplest ways to improve a computer's performance is to use a faster processor.
Every new processor generation introduces higher clock frequencies, improved instruction pipelines, wider execution units, and more sophisticated heterogeneous computing architecture. It is therefore natural to assume that replacing a processor with a faster one should proportionally improve the entire system's performance.A processor rarely performs computations in isolation. Every instruction executed by the processor depends upon data stored in memory. Instructions themselves must be fetched before they can be decoded and executed, operands must be read before arithmetic operations can begin, and computation results are frequently written back to memory. Whenever the processor needs an instruction or data value, it issues a memory request to main memory and waits for the requested information to return.If the processor executes instructions faster than the memory can supply them, the processor simply waits.A processor running at a higher clock frequency completes arithmetic operations in less time, but the access latency of the main memory does not decrease at the same rate.
Eventually, the processor spends a considerable portion of its execution time waiting for memory rather than performing useful computation.Suppose we have designed a processor running at 100 MHz, and the system performs exactly as expected.
A few years later, a newer version of the same processor becomes available, capable of operating at 500 MHz. At first glance, upgrading the processor seems like the easiest way to improve system performance. But increasing the processor clock frequency doesn’t proportionally reduce main memory latency. Although the arithmetic units can execute billions of operations per second, they remain idle while waiting for memory.Why not simply build a faster main memory?Fast memories exist, but they are significantly more expensive and still cannot eliminate every delay within the memory subsystem. Address decoding, memory buses, controllers, refresh operations, and other supporting circuitry also add latency. A different strategy is to create a small, high-speed memory called cache, designed to be accessed frequently by keeping it close to the processor. The cache acts as an intermediate storage layer between the processor and the main memory.
When the processor requests an instruction or a data value, it first checks whether a copy already exists in the cache.Memory InterleavingTo understand memory interleaving, a useful analogy comes from the firing tactics used by infantry during the 16th, 17th, and 18th centuries.
At that time, a musket required a relatively long sequence of operations before it could be fired again: pouring gunpowder, inserting the projectile, ramming it into the barrel, cleaning the air-locks, and preparing to shoot. If every soldier fired and reloaded simultaneously, the battlefield would experience long periods during which no shots could be fired.Instead, armies organized soldiers into multiple rows. While the front row fired their muskets, the rows behind them were already reloading. Once the front row stepped back to reload, the next prepared row advanced and fired.
By alternating between rows, the army maintained a nearly continuous stream of fire even though each individual musket required a significant amount of time to reload.Source: https://en.wikipedia.org/wiki/Volley_fireMemory interleaving applies the same principleInstead of placing all memory locations in a single memory bank, the memory is divided into multiple independent banks.Press enter or click to view image in full sizeThe individual access time of each memory bank does not become faster. Instead, every memory address is mapped to a specific memory bank using a deterministic addressing rule.For a memory system containing N independent banks, this simple mapping distributes consecutive memory addresses across multiple banks.Bank Number = Address mod Number_of_BanksBank Address = Address / Number_of_BanksConsider a memory subsystem consisting of four independent memory banks.Address Bank0 Bank 01 Bank 12 Bank 23 Bank 34 Bank 05 Bank 16 Bank 27 Bank 3Consecutive addresses never access the same memory bank. Every bank is still busy for exactly the same amount of time as before.Memory Interleaving is fundamentally an address mapping technique. The memory controller does not dynamically choose a bank for each request, rather the bank is determined directly from the memory address. By distributing consecutive addresses across independent banks, the memory subsystem increases its effective bandwidth while the latency of each individual memory access remains unchanged.What are SIMM and DIMM?SIMM (Single In-line Memory Module) was an earlier memory module introduced during the 1980s and widely used in Intel 286, 386, and 486 computer systems.
The memory module had electrical contacts on both sides of the printed circuit board (PCB), these contacts were electrically connected together, forming a single set of signal connections.A standard 72-pin SIMM provided a 32-bit data path, requiring two identical modules to satisfy the Pentium’s 64-bit memory bus. On systems supporting parity or ECC (Error Correction Code), each SIMM typically provided an additional 4 check bits, resulting in a 36-bit module (32-bit data + 4 check bits). When installed as a matched pair, the memory subsystem presented a 64-bit data bus together with 8 parity/ECC bits for error detection.SIMM is essentially obsolete as a current memory module standard.