How the ZX80 works

I have been expanding the instruction manual for my Minstrel ZX80 Clone to include more information on how the ZX80 works. I thought it would be good to expand on that even more here. So, how does the ZX80 work?

The Sinclair ZX80 is a low cost home computer, launched in 1980 with a price tag of £99, considerably cheaper than it's contemporary counterparts. How did they do that? Well, the first thing to know about the ZX80 is that it's main job is not to run your code. That's very much a side task. The thing it spends most of it's time doing is drawing a picture on the TV screen. And it does that by executing mainly NOP instructions.

Unlike most other computers of it's era, it doesn't have a video chip. It doesn't have any custom chips in fact. There is a Z80 CPU, a 4K ROM chip, two 1K x 4 bit static RAM chips, and seventeen 74 series TTL chips, and that's it.

Quite an achievement to make a functional computer out of that, and how it does it is very clever, and I hope to try an explain that here. I am using schematics, screenshots and logic plots from my Minstrel ZX80 clones. These follow the same design, using the same chips, and the only modern substitutions being more easily available ROM and RAM chips, and an extra TTL chip to bring the composite video closer to that required by most modern TV sets.

Oh, and I do have better keyboards available, but you can go back to a membrane if you wish.

The Z80

Well, first off, the heart of the system is the Z80 processor. This has been in continuous production since 1976, and is still going strong. Here a Z80 or Z80A is clocked at 3.25MHz (yes, more than three times faster than the 6502 in the PET, VIC20 and even the C64), although in practice, the Z80 takes more cycles per instruction that the 6502, so there's not much in it.

The /Halt, /NMI and /BusRequest control inputs to the Z80 are pulled high, leaving them in a stable state and able to be driven low to activate them. A minimal reset circuit is used, consisting of a resistor and capacitor. This holds the reset line low for around 100mS until the 1uF capacitor has charged to past the logic low level.

The Edge Connector

The ZX80 expansion edge connector is connected pretty much directly to the Z80. This exposes most of the pins of the Z80 to allow expansion to the system. It also includes power for peripherals, and a way to disable the onboard RAM. The ZX81 that followed used the same edge connector, other than a spare pin was used to also allow you to disable the onboard ROM. That has been implemented on the Minstrel ZX80 clone in the same way as the ZX81.

RAM

The ZX80 originally came with 1K of static RAM as two 2114 SRAM chips. Unlike the Z80 and all the TTL chips, the small SRAM chips are out of production. However larger modern RAM chips are available which can be addressed in the same way. In the Minstrel ZX80 clone, a 32K RAM chip has been used, as that is the most easily available (8K chips are available but are often more expensive than the 32K versions). The address decoding is identical, and is fairly minimal. If A14 is high, and the Z80 is performing a memory request, the RAM is enabled. Resistor R19 is connected between the two chips to allow the chip select signal at the chip side to be connected to the edge connector. Pulling this high will disable the internal RAM and allow an external peripheral to replace the RAM. This happened in the ZX80 and ZX81 when a 16K RAM pack was fitted, the internal 1K of RAM was disabled (a bit wasteful given the price of RAM in those days).

The initial offering for the ZX80 was a 3K expansion that used another six 2114 chips to take the RAM to 4K. Using A14 as the only decoding means the RAM is present at address 4000-7FFF and mirrored at C000-FFFF. Originally the 1K would have also been mirrored 16 times within each of those blocks, but here the full 16K block is used as RAM. The RAM chip is a 32K chip, but has the highest address line tied high, so half of the chip is not used. Due to the way the RAM is used, it would have required additional decoding logic to add the other 16K, so it is not used to maintain compatibility, and very little software would had used it.

ROM

The original ZX80 came with a 4K ROM chip. The chip select line was activated when there was a memory request and A14 was low. That meant the ROM chip was enabled from 0000-3FFF and duplicated at 8000-BFFF, and the 4K chip is mirrored 4 times in each 16K block. The ZX80 could be upgraded to ZX81 style BASIC, which came in an 8K ROM. The Minstrel ZX80 clone uses a larger EPROM, a 27C64 up to a 27C512, with multiple 8K chunks selectable via jumpers so you can have a choice of ROM versions.

Memory Map

The following table shows the memory map for four machines. An original ZX80; a ZX80 which has been upgraded with the 8K BASIC ROM and a 3K RAM pack (giving 4K in total); a ZX80 that has been upgraded with the 8K BASIC and a 16K RAM pack; and finally, the Minstrel ZX80 clone.

Address Range Original ZX80 Upgraded ZX80 ZX80 + 16K RAM Minstrel ZX80 Clone 0000-0FFF 4K ROM 8K ROM 8K ROM 8K ROM 1000-1FFF 4K ROM* 2000-2FFF 4K ROM* 8K ROM* 8K ROM* 8K ROM* 3000-3FFF 4K ROM* 4000-4FFF 1K RAM x4 4K RAM 16K RAM 16K RAM 5000-5FFF 1K RAM x4* 4K RAM* 6000-6FFF 1K RAM x4* 4K RAM* 7000-7FFF 1K RAM x4* 4K RAM* 8000-8FFF 4K ROM# 8K ROM# 8K ROM# 8K ROM# 9000-9FFF 4K ROM# A000-AFFF 4K ROM# 8K ROM# 8K ROM# 8K ROM# B000-BFFF 4K ROM# C000-CFFF 1K RAM x4# 4K RAM# 16K RAM# 16K RAM# D000-DFFF 1K RAM x4#

4K RAM# E000-EFFF 1K RAM x4# 4K RAM# F000-FFFF 1K RAM x4# 4K RAM#

* Mirrored copy # Mirrored copy used for display generation

Operating States

You may have noticed the address and data lines on the ROM and RAM chip are not simply labelled D0-D7 and A0-A15. Due to the way the ZX80 is run, there are two versions of the databus and two versions of the address bus. OK, buckle in, this is where it gets unusual.

The screen information is stored in RAM, and the ZX80 uses the way it is mirrored at the top of the address range to trigger the screen drawing hardware. It tries to execute the high mirror of the screen information (called the display file or DFILE), and this is intercepted by hardware, to trick the processor into executing a NOP or 'no operation instruction' and then step up to the next character in the display file and so on until the screen has completed. It does this in real time, generating the video output signal as it goes, when it gets to the bottom of the screen, it has a brief period where it checks to see if a key has been pressed. If not, it goes back to the top and is just in time to start drawing the next frame of the video signal. Fifty times a second, to match the 50Hz frame rate of PAL (or 60 times a second for NTSC).

If a key is pressed, it can't do anything about that and draw the screen at the same time, so it goes away to process the key press, and whilst it is doing that, the screen does not get drawn, no video is generated. When it is finished processing the key press, it goes back to drawing the screen. This generates the characteristic flashing on the screen every time you press a key. If you ask it to do something more complicated, whilst it is doing that. the screen will be off for as long as it takes, and will only be drawn again when it is finished.

The ZX81 got around this by running code in the period between the bottom one one frame of video and the top of the next, but that needed extra hardware. It is possible to do this on the ZX80 in certain circumstances, and there is an art to writing 'Flicker Free' games, when requires code to be of a fixed number of cycles exactly equalling the period between frames. More information about this (and a selection of Flicker Free Games can be found on Paul Farrow's Page).

Clock

The ZX80 clock runs at 6.5MHz, and so each clock pulse lasts 0.15uS. The standard PAL video scan line is 64uS long. The ZX80 has 32 character lines, 8 pixels per character, so each clock pulse has to generate a single pixel. That takes up just under 40uS for the section of the screen with characters on, with a synchronisation pulse at the start and blank areas either side of the characters. That is 8 clock pulses per character. The Z80 is clocked at half that speed, so each character is four Z80 clock cycles, which is how long the Z80 takes to execute a single NOP instruction. How on Earth does it do it?

The main clock is divided by two by a 74LS74 D type flip flop, which generates 3.25MHz clocks in inverted and non-inverted format, and also a buffered version driven by two open collector inverters to give a good clean fast clock pulse for the Z80. The NOP instruction takes four cycles, and during this time, the Z80 goes through several states, labelled T1 through T4.  Some instruction take a different numbers of cycles, some require additional reads to complete multipart instructions, some take longer to process etc. I'll concentrate on NOP as that is the main instruction that the Z80 in a ZX80 executes. During the first two cycles, the opcode is read from memory, and during the next two, cycles it is executed.

State Address Bus Data Bus T1 PC (code address) - T2 PC (code address) Op code T3 - - T4 - -

The Program Counter (PC) is sent to the address bus at the start of the first cycle, and the memory device that is providing the data is expected to have set the databus appropriately by the start of the second cycle. The third and forth cycles don't need to use either the address or data busses, so they could just sit idle.

The Z80 has a neat feature designed to work with dynamic RAM. DRAM (i.e. the good old 4116 chip) was much cheaper that static RAM (i.e. the 2114 used in the ZX80 or the 65526 used in the Minstrel). However, DRAM had a failing, that it is a very short term memory. The memory needs to be 'refreshed' by repeatedly accessing each bit of memory many times every second. Normally that means the system designers would have to setup a separate counter to clock through each of the addresses, and switch to that when the RAM wasn't being used by the CPU. The Z80 thoughtfully provides a refresh signal that is asserted whenever the processor is busy doing something for a few clock cycles. A separate 'R' address register steps through to the next address each time it is used, so the refreshing can be carried out as a background task. With the NOP instruction, the T3 and T4 states are used to refresh DRAM. Data is returned from the refresh operation, but it is ignored by the processor.

State Address Bus Data Bus T1 PC (code address) - T2 PC (code address) Op code T3 R (refresh address) - T4 R (refresh address) refresh data (ignored)

The designers of the ZX80 somewhat subverted this process.