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How did AMD Ryzen get 50% faster in two years?

▲ 487 points • 206 comments • by ibobev • 3w ago • HN discussion ↗

Pangram verdict · v3.3

We believe that this text is a mix of AI and human-written content.

72 %

AI likelihood · overall

Mixed
25% human-written 75% AI-generated
SEGMENTS · HUMAN 1 of 2
SEGMENTS · AI 1 of 2
WORD COUNT 474
PEAK AI % 90% · §2
Analyzed
Sep 22
backend: pangram/v3.3
Segments scanned
2 windows
avg 237 words each
Distribution
25 / 75%
human / AI fraction
Verdict
Mixed
Pangram v3.3

Article text · 474 words · 2 segments analyzed

Human AI-generated
§1 Human · 21%

People still tell me that CPUs are boring. That nothing much happens anymore. Let us look at AMD Ryzen 7 processors from 2022 to 2024: the 5800X3D (Zen 3), the 7800X3D (Zen 4) and the 9800X3D (Zen 5). They are comparable 8-core chips with 3D V-Cache. I have written about them before, in How stagnant is CPU technology? On Geekbench 6, performance went up by about 50% in two years. 2022 5800X3D Zen 3 2023 7800X3D Zen 4 2024 9800X3D Zen 5 Single-core 2,016 2,426 2,969 Multi-core 11,832 15,508 18,751 The 2024 chip is 47% faster on a single core than the 2022 chip, and 58% faster with all cores.

§2 AI · 90%

The clock did not do that. Max boost went from 4.5 GHz to 5.2 GHz, a 15% increase. 2022 Zen 3 2023 Zen 4 2024 Zen 5 Base 3.4 GHz 4.2 GHz 4.7 GHz Max boost 4.5 GHz 5.0 GHz 5.2 GHz The number of transistors is way up, by about 50%, from roughly 11 billion to 16 billion. Most of the extra transistors went into the core, not the cache. How do you turn extra transistors into extra performance? You make the core wider, and you give it more to work with. Dispatch width went from a maximum of 6 instructions per cycle to 8. The L2 cache per core doubled, from 512 KB to 1 MB. The L1 data cache went from 32 KB to 48 KB. Integer ALUs went from 4 to 6. The reorder buffer grew from 256 to 448 entries, so the processor can keep more instructions in flight and schedule them better. Zen 3 2022 Zen 4 2023 Zen 5 2024 L2 cache per core 512 KB 1 MB 1 MB L1 data cache 32 KB 32 KB 48 KB Dispatch width 6 6 8 Integer ALUs 4 4 6 Reorder buffer 256 320 448 For data parallelism (SIMD), Zen 5 is a different machine. Zen 3 and Zen 4 had four 256-bit SIMD arithmetic units. Zen 5 has four 512-bit units. Loads and stores widened the same way: two 512-bit loads per cycle, one 512-bit store. Zen 3 2022 Zen 4 2023 Zen 5 2024 SIMD arithmetic units 4 × 256-bit 4 × 256-bit 4 × 512-bit Loads per cycle 2 × 256-bit 2 × 256-bit 2 × 512-bit Stores per cycle 1 × 256-bit 1 × 256-bit 1 × 512-bit I already made the point that processors are getting wider. This is what that looks like on a desktop chip you can buy. What about the next step? Zen 6 is arriving. AMD is talking about a 256-core Epyc part (Venice) with a gigabyte of L3 cache. We do not yet know what the desktop cores will look like. It could be wild. Further reading: AMD’s 256-core Epyc 9996 ‘Venice’ (Tom’s Hardware). Published by Post navigation