GitHub - xoreaxeaxeax/asm-hall-of-shame: Racing to the bottom of CPU performance

Assembly Hall of Shame Overview Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance. 🏆 Current Champions 🏆 x86: fxrstor64 Strategy: Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions, so CPU 0's 512-byte fxrstor64 must queue behind all that contending traffic. Contender: AMD Ryzen 7 5800H ; CPU 0 — timed instruction movl $0xfcc68830, %rsi fxrstor64 %rsi ; CPUs 1..N — hammer loop against a different high-latency location movl 0xfcc68858, %eax 🏆 Score: 198,002,498,236 cycles 🏆 Time: 62 seconds Honorable Mentions A spec-violating unaligned ymm0 load that forced non-posted dword transactions from stalled GPU registers was used to break the fundamental design of System Management Mode in smiiiiiiiiiiiiiiii. vmovdqu 0xfcc003b1, %ymm0 Rules Instructions may use whatever setup is necessary, but only a single instruction is eligible to be scored. Trapped/emulated/virtualized instructions may only time the trap, not the handler. Instructions must not be interruptible. rep movs, pause, etc. are disqualified. Times are normalized based on the CPU base clock frequency. All platforms must be in their factory stock configurations - no hardware modifications. x86 Leaderboard 27. nop Strategy: nop does nothing. It opens the leaderboard accordingly. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz nop Score: 1 cycles Time: 0 nanoseconds 26. nop16 Strategy: Regular nop was too short, but how do we make nothing take longer? Try a lonnnnnng nop. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz data16 data16 data16 data16 data16 data16 data16 nopl 0x00000000(%%eax,%%eax,1) Score: 20 cycles Time: 7 nanoseconds 25. rdtsc Strategy: Just a reference instruction to get our bearings. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz rdtsc Score: 49 cycles Time: 18 nanoseconds 24. idiv Strategy: Use 128-bit dividend (rdx:rax=2:0) with small divisor to push the quotient above the ceiling imposed by sign-extension, driving the longest path through the divider microcode. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz xorq %rax, %rax ; rax = 0 (low 64 bits of dividend) movq $2, %rdx ; rdx = 2 (high 64 bits: full dividend = 2^65) movq $5, %rbx ; divisor → quotient = 2^65/5 ≈ 7.4×10^18 idivq %rbx Score: 77 cycles Time: 28 nanoseconds 23. enter Strategy: Use maximum nesting depth (31) to force 30 display-pointer loads and pushes through the microcode display-walk path. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz enter $0, $31 ; 0 bytes allocated, nesting depth 31 (maximum) Score: 112 cycles Time: 41 nanoseconds 22. fldl Strategy: Try a small denormal to trigger an FP microcode assist. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz movabsq $0x0000000000000001, %rax movq %rax, -8(%rsp) fldl -8(%rsp) Score: 133 cycles Time: 49 nanoseconds 21. clflush Strategy: Just ensure the cache line is dirty. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz clflush (%rax) ; rax -> dirty cache line resident in L3 Score: 165 cycles Time: 60 nanoseconds 20. fsin Strategy: Use exponent 0x7ff to reach 'special value' processing in microcode; positive/negative, NaN/inf doesn't seem to make a difference, go with QNaN. Contender: Intel(R) Core(TM) i7-8559U CPU @ 2.70GHz movabsq $0x7fffffffffffffff, %rax movq %rax, -8(%rsp) fldl -8(%rsp) fsin Score: 257 cycles Time: 94 nanoseconds 19.